Jeyavijayan Rajendran
Graduate Student
Department of Electrical and Computer Engineering
Polytechnic University
6 Metrotech Center, Brooklyn, NY 11201
Phone: (718) 260-4011
RESEARCH INTERESTS
Nanoscale architectures
Trusted hardware design
ADVISORS
EDUCATION
B.E. in Electronics and Communication Engineering, Anna University, Chennai, India, 2008
M.S. in Computer Engineering, NYU-Poly, New York, USA, 2010
Ph.D. in Electrical Engineering, NYU-Poly, New York, USA, In progress
HONORS AND AWARDS
Third place in IT Security for the next generation in Kaspersky American Cup, Nov 2011
Summer intern at Quantum Research Labs in Hewlett-Packard, June 2011 - Sep 2011
Myron M. Rosenthal Award for Best MS Academic Achievement in ECE Department, NYU-Poly, May 2011
Best Student Paper Award in IEEE International Conference on VLSI Design, Jan 2011
First place in Cyber Security Awareness Week - Embedded Systems Challenge, Nov. 2009
Research Fellowship from Fall 2009 to Fall 2011
Teaching Assisstantship from Fall 2010 to Fall 2011
Best Outgoing Student Award, (Undergraduate) May 2008
PUBLICATIONS
PATENTS
P1. J. Rajendran, V. Jyothi, O. Sinanoglu, and R. Karri, is going to file for patent entitled Reconfiguring functional path into Trojan detecting Ring oscillators.
BOOK CHAPTERS
B1. R. Karri, J. Rajendran, and K. Rosenfeld, Trojan Taxonomy, A Book chapter in Hardware Security and Trust.
JOURNALS AND MAGAZINES
J6. H. Manem, J. Rajendran, and G.S. Rose, Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array, accepted for publication in IEEE Transactions on Circuits and Systems-I (TCAS-I).
J5. H. Manem, J. Rajendran and G.S. Rose, Design Considerations for Multi-Level CMOS/Nano Memristive Memory, accepted for publication in ACM Journal of Emerging Technologies in Computing (JETC).
J4. G.S. Rose, H. Manem, J. Rajendran, R. Karri and R. Pino, Leveraging Memristive Systems in the Construction of Digital Logic Circuits, accepted for publication in Proceedings of the IEEE (IEEEProc).
J3. J. Rajendran, H. Manem, R. Karri and G.S. Rose, An Energy-Efficient Memristive Threshold Logic Circuit, accepted for publication in IEEE Transactions on Computers (TComp).
J2. M. Tehranipoor, H. Salmani, X. Zhang, X. Wang, R. Karri, J.Rajendran, and K. Rosenfeld, Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges, Computer Magazine, July 2011 (Computer Magazine).
J1. R. Karri, .Rajendran, K. Rosenfeld, and M. Tehranipoor, Trustworthy Hardware: Identifying and Classifying Hardware Trojans, Computer Magazine, Oct. 2010 (Computer Magazine).
CONFERENCE PAPERS
C12. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Security Analysis of Logic Obfuscation, accepted in Design Automation Conference, May 2012 (DAC'12).
C11. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Applying IC Testing Concepts to Secure ICs, accepted in Government Microcircuit Applications and Critical Technology, March 2012 (GOMACTECH'12).
C10. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Fault-analysis based Logic Encryption, accepted in Design Automation and Test in Europe, March 2012 (DATE'12).
C9. J. Rajendran, V. Jyothi, and R. Karri, Red team blue team approach to hardware trust assessment: The embedded systems challenge experience, accepted in IEEE International Symposium on Computer Design, Oct 2011 (ICCD'11).
C8. J. Rajendran, R. Karri, and G.S. Rose, Parallel Memristors: Improving Variation Tolerance in Memristive Digital Circuits, in the Proceedings of IEEE International Symposium on Circuits and Systems, May 2011 (ISCAS'11).
C7. J. Rajendran, V. Jyothi, O. Sinanoglu, and R. Karri, Reconfiguration of functional logic into Trojan Detecting Ring Oscillators and Test-for-Trust Cost analysis, in the Proceedings of IEEE VLSI Test Symposium, May 2011. (VTS'11).
C6. J. Rajendran, H. Manem, R. Karri and G.S. Rose, An Approach to Tolerate Process Related Variations in Memristor-based Applications, to appear in Proceedings of IEEE Symposium on VLSI Design, Jan. 2011. (Best Student Paper Award) (VLSIDesign'11).
C5. J. Rajendran, H. Manem, R. Karri and G.S. Rose, Memristor based Programmable Threshold Logic Array, in the Proceedings of IEEE Symposium on Nanoscale Architectures, June 2010 (NanoArch'10).
C4. J. Rajendran, H. Borad, S. Mantravadi and R. Karri, SLICED: A Slide based Concurrent Error Detection Technique for Symmetric Block Ciphers, in the Proceedings of IEEE Symposium on Hardware Oriented Security and Trust, June 2010 (HOST'10).
C3. J. Rajendran, J. Jimenez, E. Gavas, V. Padman and R. Karri, A comprehensive taxonomy of hardware Trojans, in the Proceedings of IEEE Symposium on Circuits and Systems, May 2010 (ISCAS'10).
C2. J. Rajendran, H. Manem and G.S. Rose, NDR based threshold logic fabric with memristive synapses, in the Proceedings of IEEE-NANO, 2009 (NANO'09).
C1. S. Chandrasekharan, J. Rajendran and A. Annamalai, Data driven security alarm model for embedded applications, Proceedings of IEEE International Conference on Computing, Communication and Networking, 2008 (ICCCN'08).